I am a
lecturer at Brunel University London.
My research is on formal logics and verification methods for concurrent and real-time systems.
I received a BSc in Computer Science and Mathematics and a BSc (Hons) in Logic and Computation, both from Victoria University of Wellington, New Zealand. In 2009, I completed a PhD on formal derivations of concurrent algorithms at the University of Queensland, Australia. After this, I held postdoctorate positions at the University of Queensland and then at the University of Sheffield.
Here is a talk I recently gave at ECOOP 2015.
REFINE 2015, PDP 2015.
My list of publications is here, DBLP page is here, and Google Scholar page is here.
Current research funding
Some previous research and collaborators
E-mail: Brijesh.Dongol [[at]] brunel [[dot]] ac [[dot]] uk
You can find me in STJN 105