I am a lecturer at Brunel University London.

My research is on formal logics and verification methods for concurrent and real-time systems.

I received a BSc in Computer Science and Mathematics and a BSc (Hons) in Logic and Computation, both from Victoria University of Wellington, New Zealand. In 2009, I completed a PhD on formal derivations of concurrent algorithms at the University of Queensland, Australia. After this, I held postdoctorate positions at the University of Queensland and then at the University of Sheffield.

Here is a talk I recently gave at ECOOP 2015.

Program committees
REFINE 2015, PDP 2015.

My list of publications is here, DBLP page is here, and Google Scholar page is here.

Current research funding
  • 2015. EPSRC (£122,774).
    Verifiably correct high-performance concurrency libraries for multi-core computing systems
  • 2015-16. Brunel University (£5,000).
    Verifying energy-aware networks on chip systems
  • 2015-16. Brunel University New Staff Grant (£10,000)

Some previous research and collaborators
Completed projects
  • 2012. University of Sheffield SEED Grant (£2,500).
    Verifiable real-time controllers with multi-timescale requirements
  • 2009. University of Queensland New Staff Research Start-Up Fund (AU$11,977).
    A logic for reasoning about progress properties of teleo-reactive programs
  • 2009. The University of Queensland ResTeach Award (AU$18,428)

Contact details

E-mail: Brijesh.Dongol [[at]] brunel [[dot]] ac [[dot]] uk

You can find me in STJN 105

Mailing address:
Department of Computer Science
Brunel University London
Middlesex UB8 3PH