I am a
lecturer at Brunel University London.
My research is on formal techniques and verification methods for concurrent and real-time systems. This includes concurrent objects, transactional memory and associated correctness conditions; weak memory models; algebraic techniques; and hybrid systems.
I received a BSc in Computer Science and Mathematics and a BSc (Hons) in Logic and Computation, both from Victoria University of Wellington, New Zealand. In 2009, I completed a PhD on formal derivations of concurrent algorithms at the University of Queensland, Australia. After this, I held postdoctorate positions at the University of Queensland and then at the University of Sheffield.
REFINE 2018 (co-chair), REFINE 2015, PDP 2015.
My list of publications is here - most recent publications include additional links to mechanisation. My DBLP page is here, and Google Scholar page is here.
Post docs (previous)
Some previous research and collaborators
Here is a talk I gave at ECOOP 2015.
E-mail: Brijesh.Dongol [[at]] brunel [[dot]] ac [[dot]] uk
You can find me in STJN 105